Appliance Electronics & Control Boards calculator

ICT Test Capacity Calculator Calculator

In-circuit test capacity can constrain high-volume appliance control board production when fixture cycle time, debug time, and retest volume grow. This calculator estimates usable ICT output for control boards after tester availability and passable test yield are applied.

What this calculator does

  • Estimate in-circuit test capacity for appliance control boards from boards per fixture cycle, available cycles, tester uptime, and passable test yield.
  • a test engineer or production planner needs to verify whether ICT fixtures can keep up with PCB assembly output
  • Returns the good-board test capacity expected from ICT fixtures in the selected operating period.

Formula used

  • Gross ICT board capacity = boards tested per fixture cycle × available ICT fixture cycles
  • Usable ICT test capacity = gross capacity × ICT tester uptime × first-pass ICT yield

Inputs explained

  • Boards tested per ICT fixture cycle: undefined
  • Available ICT fixture cycles: undefined
  • ICT tester uptime: undefined
  • First-pass ICT yield: undefined

How to use the result

  • Use it to size ICT fixtures, approve appliance board ramps, assess tester downtime, or compare fixture-cycle-time improvements.
  • The estimate does not model detailed test-step timing, probe maintenance, false failures, fixture changeovers, debug queues, or retest loops.

Common questions

  • What is an ICT fixture cycle? It is one complete clamp, probe, measurement, and release cycle for the board or panel configuration used by the fixture.
  • Should failed boards be counted as capacity? Failed boards consume tester time, but the usable capacity result removes the first-pass failures so planners can see good output.
  • What does ICT tester uptime include? Include expected downtime for maintenance, probe cleaning, fixture issues, software faults, and unavailable operators if those stop testing.
  • How can I use this result? Use it to decide whether another fixture, second tester, cycle-time reduction, or debug process improvement is needed.

Last reviewed 2026-05-12.