Formulas

How to Calculate SMT Throughput, Test Yield, and Panelization for Appliance Control Boards

Step by step worked examples for the core appliance control board calculations: SMT throughput, first pass yield and DPMO, rolled throughput yield, panelization, attrition, and firmware programming load.

Every appliance control board program runs on the same handful of calculations: SMT line throughput, first pass yield at each test gate, rolled throughput yield, panelization yield, component attrition, and programming load. Miss any of them by a few percent and your capacity plan, tester count, and material buy all drift. This guide works each formula with real units on a representative board: a 120 mm by 180 mm appliance controller with 385 placements, roughly 950 solder joints, an in circuit test, and a 45 second functional test. The SMT Line Throughput Calculator and Functional Test Yield Calculator run the same equations if you want the arithmetic checked.

SMT throughput starts with rated placement speed, then derates it. Boards per hour equals net components per hour divided by placements per board. A placer rated 78,000 CPH under IPC 9850 conditions typically delivers 55 to 65 percent of that in production, so use 0.60 x 78,000 = 46,800 net CPH. For 385 placements per board: 46,800 / 385 = 121.6 boards per hour at the placer. Then apply line utilization. Three changeovers per 480 minute shift at 20 minutes each removes 60 minutes, so utilization is 420 / 480 = 87.5 percent, giving about 106 boards per hour effective. Rated speed comes from the machine spec sheet; the derate factor comes from your MES placement logs.

First pass yield is good units on the first attempt divided by units tested, using serialized data so retests never count. If ICT sees 1,000 boards and 978 pass without any repair, ICT FPY is 97.8 percent. To compare boards of different complexity, convert to defects per million opportunities: DPMO = defects / (units x opportunities per board) x 1,000,000. Count each component and each solder joint as an opportunity: 385 components plus 950 joints gives 1,335 opportunities. Thirty defects across those 1,000 boards yields DPMO = 30 / (1,000 x 1,335) x 1,000,000 = 22.5. The Functional Test Yield Calculator does both conversions from raw pass and fail counts.

Rolled throughput yield multiplies first pass yield across every gate: RTY = FPY at AOI x FPY at ICT x FPY at functional test. With 98.5, 97.8, and 97.2 percent, RTY = 0.985 x 0.978 x 0.972 = 0.936. To deliver 10,000 good boards with fallout scrapped, launch 10,000 / 0.936 = 10,684 boards. Final yield after rework often reads 99 percent and hides three rework loops, so always size launch quantity and buffer stock from RTY, never final yield. Pull each gate FPY from station logs keyed by serial number over at least four weeks of production to smooth out lot to lot effects.

Test capacity per station is 3,600 seconds divided by cycle time, where cycle time is test time plus handling. ICT at 35 seconds of test plus 10 seconds of load and unload gives 3,600 / 45 = 80 boards per hour per fixture. Stations needed = line demand / (station capacity x availability). With 106 boards per hour arriving from SMT and 90 percent tester availability: 106 / (80 x 0.90) = 1.47, so install two fixtures. Functional test at 45 plus 12 seconds runs 63.2 boards per hour, needing 106 / (63.2 x 0.90) = 1.86, again two stations. The ICT Test Capacity Calculator sizes both gates from these inputs.

Panelization yield has two parts: material utilization and X-out loss. Utilization = (board area x boards per panel) / panel area. Four 120 x 180 mm boards on a 380 x 420 mm panel: (0.0216 m2 x 4) / 0.1596 m2 = 54.1 percent; the rest is rails, tooling strips, and spacing. Effective boards per panel = boards per panel x (1 minus X-out rate). At a 2 percent X-out rate from the bare board fabricator, 4 x 0.98 = 3.92 usable boards per panel, so a 10,000 board order needs 2,552 panels, not 2,500. The Panelization Yield Calculator compares candidate layouts before you commit fab tooling.

Component attrition sets how many extra parts to buy. Extra parts = board quantity x placements of that part x attrition rate for its class. Typical planning rates: 0.3 to 0.5 percent for 0201 and 0402 passives, 0.1 to 0.2 percent for larger discretes, and 0.02 to 0.05 percent for fine pitch ICs. A 10,000 board run with 280 small passives per board at 0.4 percent needs 10,000 x 280 x 0.004 = 11,200 extra passives, about 1.4 full reels of 8,000 pieces. Reconcile planned rates against actual feeder reject counts quarterly; the Component Attrition Cost Calculator converts the gap into dollars per build.

Firmware programming load determines whether you program inline or offline. Inline stations needed = (line rate x programming seconds) / 3,600. At 106 boards per hour and a 28 second write and verify cycle: (106 x 28) / 3,600 = 0.82, so one inline station holds, but only until the image grows. Doubling image size roughly doubles write time and pushes the requirement to 1.65 stations. Offline, an 8 site gang programmer delivers 8 x (3,600 / 28) = 1,028 devices per hour before handling losses. The Firmware Programming Load Calculator runs both scenarios so image growth never surprises the line mid program.

Published 2026-07-02.