Calculations

How to Calculate Assembly Time, Test Capacity, and Yield in Gaming Hardware Production

Work through the five core production formulas for gaming and entertainment hardware, from cabinet standard time to rolled throughput yield, with real units and worked examples.

Gaming and entertainment hardware production lives or dies on five numbers: assembly standard time, test station capacity, first pass yield, firmware flashing throughput, and calibration station load. Each one feeds a scheduling or staffing decision, and each one is a short formula with three or four inputs you already have in your MES or time study data. This guide works every formula with real units and worked examples pulled from arcade cabinet, console peripheral, and pinball lines. Grab a stopwatch, a shift calendar, and last month's test logs, and you can compute all five in an afternoon.

Start with standard time for cabinet assembly. Break the build into elements, time each one, then apply an allowance: Standard Time = sum of element times x (1 + PFD allowance), where PFD covers personal time, fatigue, and unavoidable delay, usually 12 to 15 percent. Example: an upright arcade cabinet with 24 elements timed at 41.6 minutes total gets 41.6 x 1.15 = 47.8 standard minutes. Divide by crew size for elapsed time: a two person crew delivers a cabinet every 23.9 minutes if the work balances cleanly. The Cabinet Assembly Time calculator runs this math and flags stations loaded above 95 percent of takt.

Test capacity uses one formula for every station type: Capacity per shift = (stations x available minutes x utilization) / test cycle time. Available minutes come from the shift calendar minus breaks and meetings, typically 435 to 450 of a 480 minute shift. Utilization of 80 to 85 percent accounts for loading, retest, and micro stoppages. Worked example: 4 display inspection stations, 450 available minutes, 85 percent utilization, and a 6.5 minute cycle gives (4 x 450 x 0.85) / 6.5 = 235 displays per shift. The Display Test Capacity and Audio Test Capacity calculators apply the same structure with cycle time presets for each test type.

Yield math has two levels. First pass yield for a single stage is FPY = units passing on the first attempt / units tested. Rolled throughput yield across the line is RTY = FPY1 x FPY2 x FPY3 and so on for every stage. Example from a controller PCB line: in circuit test at 98.5 percent, functional test at 97.2 percent, and calibration at 99.1 percent gives RTY = 0.985 x 0.972 x 0.991 = 0.949, so you must launch 1,054 boards to ship 1,000 good ones. Pull pass and fail counts from test logs over at least 20 production days, and let the PCB Test Yield calculator compute FPY, RTY, and required launch quantity.

Firmware flashing throughput is a cycle time problem with parallelism. Units per hour = (3600 / (flash seconds + handling seconds)) x sockets per gang programmer. Flash time depends on image size and interface: a 128 MB image over USB 2.0 at roughly 20 MB/s takes about 90 seconds including verify. Add 15 seconds of load and unload, and an 8 socket gang delivers (3600 / 105) x 8 = 274 units per hour. If demand is 1,800 units per 7.5 hour shift, you need 1800 / (274 x 7.5) = 0.88 programmers, so one machine with headroom. The Firmware Flashing Throughput calculator handles image size, interface speed, and verify passes.

Controller calibration load converts demand into required stations: Stations = (daily demand x calibration cycle minutes) / (available minutes x utilization). A joystick and trigger calibration cycle of 3.0 minutes, demand of 1,200 controllers per day, 450 available minutes, and 85 percent utilization gives (1200 x 3.0) / (450 x 0.85) = 9.4 stations, so plan 10 and cross train two floaters for absence coverage. Round up, never down, because a station short at full load builds roughly 1 hour of queued WIP for every 6 percent of overload across a shift. The Controller Calibration Load calculator does the rounding and shows load per station.

Every input has a proper source. Element times come from stopwatch studies of at least 10 cycles or MES timestamps, not operator estimates, which run 15 to 25 percent optimistic. Test cycle times come from the last 30 days of station logs, using the median rather than the mean to strip outlier retests. Yields come from first attempt pass counts only; counting retested passes inflates FPY by 2 to 4 points. Recalculate quarterly, or after any firmware image change, fixture rebuild, or product revision. Once the five numbers are current, they feed directly into quoting and KPI tracking, which we cover in separate guides.

Published 2026-07-02.