How do you calculate ICT test time?

Divide boards requiring ICT by the tested-board rate for a base cycle time, then multiply by one plus the debug and retest allowance. With 850 boards at 5.5 boards/min and an 18% allowance, base time is about 155 min and estimated time is about 182 min.

Why add a debug and retest allowance?

Because the raw rate assumes every board passes first time. Real ICT runs include failures that get debugged and re-run through the fixture, so the 18% allowance here adds about 28 minutes to the 155-minute base for a realistic 182 minutes.

What is a typical ICT tested-board rate?

It depends heavily on test coverage and node count, but loaded boards commonly run a few boards per minute on a bed-of-nails fixture. The 5.5 boards/min default suits a moderate-coverage board with reasonable fixture access.

What is a good debug and retest allowance?

Stable, high-yield programs often run 5-15%; new or troubled boards can need 20-30% or more. Pick the allowance from your own recent first-pass yield rather than a generic guess.

ICT test time vs functional test time, which is longer?

ICT is usually faster per board than functional test because it checks nodes electrically rather than exercising the product, but ICT's debug tail can close the gap. Use this calculator for the ICT leg and a separate functional estimate for the rest.

How do I shorten ICT test time?

Raise first-pass yield upstream to shrink the debug allowance, improve fixture contact to cut retries, and prune redundant test steps. Cutting the allowance from 18% to 10% on this batch would save roughly 12 minutes.

Electronics Manufacturing calculator

ICT Test Time Calculator

ICT test time is the total minutes an in-circuit test station needs to clear a batch of boards, including the realistic overhead of debugging and retesting failures. Test engineers and production schedulers use it to slot ICT into a shift, size operator coverage, and predict when boards will reach functional test downstream. It matters because ICT is frequently the slowest test step on an SMT line, and the debug-and-retest tail is what people underestimate: the raw tested-board rate looks fast until first-pass failures bounce back through the fixture. Adding an honest allowance turns a wishful cycle time into a schedulable number.

What this calculator does

Estimate in-circuit test minutes from boards to test, tested-board rate, and debug/retest allowance.
a test engineer is scheduling ICT tester time for a PCB assembly lot
It estimates total ICT test time for a batch by dividing boards by the tested-board rate and inflating for a debug and retest allowance.

Formula used

Base ICT cycle time = boards requiring ICT ÷ ICT tested-board rate
Estimated ICT test time = base ICT cycle time × debug and retest allowance factor

Inputs explained

Boards requiring ICT:
ICT tested-board rate:
Debug and retest allowance:

How to use the result

Use it when scheduling an ICT run, sizing test coverage for a batch, or estimating when boards reach functional test.
The allowance is a flat percentage; a batch with clustered failures or a fixture problem can blow well past the modeled time.

Current U.S. benchmarks

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Common questions

How do you calculate ICT test time? Divide boards requiring ICT by the tested-board rate for a base cycle time, then multiply by one plus the debug and retest allowance. With 850 boards at 5.5 boards/min and an 18% allowance, base time is about 155 min and estimated time is about 182 min.
Why add a debug and retest allowance? Because the raw rate assumes every board passes first time. Real ICT runs include failures that get debugged and re-run through the fixture, so the 18% allowance here adds about 28 minutes to the 155-minute base for a realistic 182 minutes.
What is a typical ICT tested-board rate? It depends heavily on test coverage and node count, but loaded boards commonly run a few boards per minute on a bed-of-nails fixture. The 5.5 boards/min default suits a moderate-coverage board with reasonable fixture access.
What is a good debug and retest allowance? Stable, high-yield programs often run 5-15%; new or troubled boards can need 20-30% or more. Pick the allowance from your own recent first-pass yield rather than a generic guess.
ICT test time vs functional test time, which is longer? ICT is usually faster per board than functional test because it checks nodes electrically rather than exercising the product, but ICT's debug tail can close the gap. Use this calculator for the ICT leg and a separate functional estimate for the rest.

Last reviewed 2026-05-12.