Advanced Packaging and Test KPIs: Benchmark Ranges and How to Hit Them
The KPIs that decide an advanced packaging and test line: how to measure yield, utilization, first pass rate and OEE, the levers that move them, and which figures have a cited source.
Use a benchmark as a reference point for spotting a gap worth investigating, not as a target. On a packaging and test line the KPIs compound: assembly yield sets how many units reach test, first pass yield sets how much tester time goes to retests, and utilization spreads the fixed cost of testers and ovens.
Every figure shows its basis. A superscript number links to a public source in the Sources list, and the sentence gives that source's context. A figure marked no cited source is kept exactly as originally published because no public source stating it has been verified, so treat it as illustrative.
At a glance
Advanced packaging and test KPI benchmarks at a glance
Words in parentheses describe each figure as the original guide or the cited source framed it. Not stated means the guide gives no figure for that column. The injury rate is cases per 100 full-time workers.
Method: How the figures in this guide are sourced
A figure with a superscript number is stated by the cited source, listed under Sources with its publisher, location in the document and access date. The cited OEE figures are cross-industry benchmarks, not packaging-specific ones, and the sentence says so. A figure marked no cited source is kept exactly as originally published because no public source stating it has been verified. It is illustrative, not measured industry data. Worked examples show arithmetic only and are not benchmarks.
Package assembly yield
Package assembly yield is the headline KPI. Mature, high-volume flip chip and wire bond lines run 99.0 to 99.7 percent per package no cited source; anything below 98.5 percent on a stable product signals a process or material problem no cited source.
Chiplet and 2.5D modules run lower because yield compounds across die. World-class multi-die module yield is around 92 to 96 percent no cited source, and typical new-ramp lines run 85 to 90 percent no cited source.
How to measure
Divide good packages out by packages started at each assembly step.
Multiply the step yields to get the compound number for the module.
Compare step yields side by side so you can see which stage is bleeding the composite.
What moves it
Process and material control on a stable product.
Known-good-die quality before multi-die assembly, since yield compounds across die.
Fixing the weakest step first, because it caps the compound number.
First pass test yield at final test is the fastest signal of upstream health. World-class first pass yield sits at 98 to 99.5 percent on a mature part no cited source; a healthy ramp is 94 to 97 percent no cited source.
Below 92 percent means bin analysis is overdue no cited source. Drive the top three failing bins to root cause.
Watch the retest recovery gap. For example, if final yield is 99 percent but first pass is 93 percent, retest recovers 6 points of yield, yet all 7 percent of units that failed the first insertion go back on the tester, so retests cost at least 7 percent more tester insertions.
How to measure
Divide good first insertions by total first insertions.
Track it by bin, not only as one number.
Report final yield after retest alongside it, so the gap stays visible.
What moves it
Root cause on the top three failing bins.
Upstream assembly fixes, since final test mostly reports what happened earlier.
Closing the first-pass-to-final gap to reclaim tester hours.
Tester and handler utilization decides your cost per unit more than raw speed. World-class final test cell utilization is 80 to 88 percent of scheduled time no cited source; typical is 65 to 78 percent no cited source, and lot changeovers, index jams and contactor cleaning eat the difference.
Wafer sort prober utilization benchmarks similarly at 78 to 85 percent world-class no cited source. Compare nameplate UPH (units per hour) against actual: if the ratio is under 0.75, the problem is scheduling and material flow, not the tester program no cited source.
For wafer sort, also track touch-down efficiency: the wafer touch-downs needed to test every die, relative to the theoretical minimum. In the IEEE Heterogeneous Integration Roadmap's example, a 10-site probe card that needs 110 touch-downs instead of the ideal 100 to test 1,000 die runs at roughly 90 percent5.
How to measure
Divide productive tester hours by scheduled hours for each final test cell.
Do the same for each wafer sort prober.
Divide actual UPH by nameplate UPH for each cell.
What moves it
Faster lot changeovers.
Fewer handler index jams.
Planned contactor cleaning instead of stops when yield drops.
Scheduling and material flow that keep testers fed.
Test parallelism efficiency is a KPI in its own right. On a 16-site handler, effective parallelism should exceed 90 percent no cited source, meaning you get more than 14.4 sites of real throughput (0.90 x 16). Below 85 percent points to tester resource contention or thermal soak limits no cited source.
For example, raising parallelism from 8 to 16 sites at 92 percent efficiency takes effective sites from 7.4 to 14.7, which halves tester time per unit and nearly halves per-unit test cost once the higher interface and load-board cost is counted.
The IEEE Heterogeneous Integration Roadmap measures this differently, as multi-site efficiency based on how test time grows with site count. It calls 98 percent adequate for testing two and four sites but says much higher efficiency is needed for 32 sites, where 98 percent stretches a 10-second single-site test to 16.4 seconds5. Keep the two definitions apart when you compare figures.
How to measure
Divide real throughput in effective sites by the number of sites on the handler.
Record the definition you use, throughput-based or test-time-based, next to every figure.
Recheck it whenever the test program or load board changes.
What moves it
Test program optimization.
Load-board resource sharing.
Thermal soak limits, rather than buying faster testers.
Burn-in occupancy and effective board loading tell you if you are paying for empty oven slots. World-class burn-in board utilization runs above 90 percent of socket capacity no cited source, with oven occupancy above 88 percent of available hours no cited source.
Typical operations sit at 75 to 85 percent because of partial-lot burn-ins and recipe changeovers no cited source. Consolidating partial lots and standardizing recipes can lift occupancy 8 to 12 points no cited source and directly lowers the burn-in cost carried per device.
How to measure
Divide occupied sockets by total sockets across the oven fleet.
Divide oven hours in use by available hours.
Log partial-lot runs and recipe changeovers as the causes of lost occupancy.
Overall equipment effectiveness (OEE) ties it together for the whole cell: availability times performance times quality. The world-class benchmark traced to Nakajima's total productive maintenance work is OEE above 85 percent, which a 2022 peer-reviewed study tabulates as availability above 90 percent, performance above 95 percent and quality above 99.9 percent3.
The Lean Enterprise Institute illustrates the same target with availability at 90 percent, performance at 95 and quality at 99, which multiply to 84.6 percent OEE6. These are generic discrete-manufacturing benchmarks, not ones measured on packaging and test lines.
Typical brownfield lines land at 55 to 70 percent OEE1, 2. Those figures are cross-industry: a Chalmers study of 23 Swedish companies found a median OEE of 70 percent and an average of 651, and Vorne, an OEE vendor, observes that most manufacturers score closer to 60 percent2.
The usual culprit is availability lost to changeovers and unplanned bonder or handler downtime.
For example, a 10 point OEE gain on a line rated at 4,400 UPH is roughly 440 more good units per hour (0.10 x 4,400) with no new capital.
How to measure
Multiply availability, performance against rated UPH, and quality for the whole cell.
Log every changeover and unplanned bonder or handler stop against availability.
State whether a UPH figure is the rated rate or current output before comparing gains.
Wire bond and die attach process KPIs deserve their own targets. Bond first pass yield should exceed 99.5 percent no cited source, with non-stick-on-pad rates under 50 parts per million no cited source.
Die attach void percentage under bond pads should stay under 5 percent by area for thermal parts, tighter for power devices no cited source. If effective bonds per second are below 10 on a machine rated at 12 to 14 no cited source, look at material handling and inspection dwell rather than bonder head speed.
How to measure
Divide good bonds on the first pass by bonds made.
Count non-stick-on-pad events per million bonds.
Measure die attach voiding as a share of the area under the bond pads.
Track bonds per hour against nameplate for each bonder.
What moves it
Material handling that keeps the bonder fed.
Shorter inspection dwell.
Die attach process control, held tighter for power devices.
Sequence the levers by leverage, and measure every KPI with one fixed definition so your own trend is readable.
First stabilize compound assembly yield, because every point recovered flows straight to cost per good unit and to test capacity.
Second, close the first-pass-to-final gap to reclaim tester hours.
Third, push parallelism and utilization to spread fixed tester and oven cost.
Review the KPIs together, since a gain in one changes the load on the next.
A line moving assembly yield from 96 to 98.5 percent, first pass test yield from 93 to 97 percent, and tester utilization from 70 to 82 percent will see per-unit cost fall high single digits with zero added equipment no cited source. That is the real payoff of watching these KPIs together.
Keep safety on the same scorecard. U.S. semiconductor device plants recorded 0.8 recordable injuries and illnesses per 100 full-time workers in 2024, against 2.7 across all manufacturing4.
World-Class OEE: Set Targets To Drive Improvement. Vorne Industries (OEE.com). Sections 'What Is World-Class OEE?', 'TPM and World-Class OEE', 'Some Perspective on World-Class OEE'. Accessed September 30, 2026.
Anatomization of the overall equipment effectiveness (OEE) for various machines in a tool and die shop. Journal of Intelligent Manufacturing and Special Equipment, Vol. 3 No. 1, pp. 97-105 (Emerald, CC BY 4.0), DOI 10.1108/JIMSE-01-2022-0004. published 2022. p. 101 (PDF p. 5): sentence "Seiichi Nakajima included the above four “world-class” numbers." and Table 1 "The world-class OEE factor"; p. 103 (PDF p. 7): "worldwide threshold of >85% set by the Japan Institute of Plant Maintenance (JIPM)". Accessed September 30, 2026.